1. Field of Invention
The invention relates to a method for modifying the composition of a trap layer structure using a gas cluster ion beam (GCIB) and, in particular, a method for infusing material in a charge trap layer using a GCIB.
2. Description of Related Art
A typical semiconductor memory device utilized during microprocessor operation is a volatile type of memory device. However, in the event of power interruption, the data stored in such a memory device is lost. An alternative to the volatile type of memory device is a non-volatile type memory device. The non-volatile type memory device retains stored information even when power is terminated. To achieve this function, non-volatile type memory devices may be supplied with a floating layer upon which charges may be stored or removed depending on a program or erase status of the device. Two types of such floating layer devices may include a floating gate type device and a floating trap type device.
A floating gate type device may include a conductive gate layer that floats due to its isolation by a surrounding insulating layer. The floating gate may be isolated from a substrate channel located below and from a control gate located above. The floating gate type device may be, respectively, programmed and erased by storing and removing charges as free carriers on the conductive floating gate. A floating trap type device may include a non-conductive layer that may be floating between a substrate channel and a control gate. The floating trap type device may be programmed and erased by storing and removing charges in traps in the non-conductive floating layer.
A known type of floating trap type device may be a silicon-oxide-nitride-oxide-semiconductor (SONOS) device. A SONOS device may include a tunneling insulating layer on a substrate, a charge trap layer on the tunneling layer, a blocking insulation layer on the charge trap layer, and a gate electrode on the blocking insulation layer. The substrate may include a P-type silicon substrate having N-type impurity layers formed on either side of the gate electrode as a source and drain. Thermal oxide may be used to form the tunneling layer and silicon nitride may be used as the charge trap layer. During operation, charges may be moved to and from the charge trap layer from and to the substrate in order to program and erase the memory cell.
To address certain shortcomings of SONOS technology, a floating trap type memory device including a metal (e.g., tantalum) layer, a high-k dielectric (e.g., aluminum oxide) layer, and a nitride-oxide-semiconductor layered structure (TANOS) has been introduced. In a TANOS device, a gate may be made of a metal, for example tantalum, and a blocking layer may be made of a high-k dielectric material, for example, aluminum oxide. The use of a high-k dielectric material as a blocking layer may be a significant feature of the TANOS architecture. Additional features of a TANOS device may include a high work function layer and a barrier metal layer as part of the gate electrode structure.
One emerging challenge facing non-volatile memory fabrication includes the ability to adjust and/or tune the material properties of the trap layer structure to optimize charge retention in the trap layer structure.